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HPCA
2008
IEEE
14 years 7 months ago
Performance-aware speculation control using wrong path usefulness prediction
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Pa...
ASPLOS
1998
ACM
13 years 11 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
IPPS
2002
IEEE
14 years 13 days ago
Implementing the NAS Benchmark MG in SAC
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
Clemens Grelck
DEBS
2010
ACM
13 years 11 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
IWMM
2011
Springer
217views Hardware» more  IWMM 2011»
12 years 10 months ago
On the theory and potential of LRU-MRU collaborative cache management
The goal of cache management is to maximize data reuse. Collaborative caching provides an interface for software to communicate access information to hardware. In theory, it can o...
Xiaoming Gu, Chen Ding