386 search results - page 65 / 78 » Informing Memory Operations: Providing Memory Performance Fe... |
HIPC
1999
Springer
13 years 11 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Over the last twenty years the interfaces for accessing persistent storage within a computer system have remained essentially unchanged. Simply put, seek, read and write have de�...
MJ
2008
13 years 7 months ago
2008
This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reco...
CN
2006
13 years 7 months ago
2006
In this article, we propose a new single-rate end-to-end multicast congestion control scheme called Explicit Rate Multicast Congestion Control (ERMCC) based on a new metric, TRAC ...
ICS
2003
Tsinghua U.
14 years 21 days ago
2003
Tsinghua U.
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...