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» Input validation analysis and testing
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JIPS
2010
107views more  JIPS 2010»
13 years 2 months ago
Incremental Model-based Test Suite Reduction with Formal Concept Analysis
Test scenarios can be derived based on some system models for requirements validation purposes. Model-based test suite reduction aims to provide a smaller set of test scenarios whi...
Pin Ng, Richard Y. K. Fung, Ray W. M. Kong
ITC
1997
IEEE
107views Hardware» more  ITC 1997»
13 years 12 months ago
On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
Benoît R. Veillette, Gordon W. Roberts
IEEEPACT
2002
IEEE
14 years 21 days ago
Workload Design: Selecting Representative Program-Input Pairs
Having a representative workload of the target domain of a microprocessor is extremely important throughout its design. The composition of a workload involves two issues: (i) whic...
Lieven Eeckhout, Hans Vandierendonck, Koenraad De ...
PTS
2000
75views Hardware» more  PTS 2000»
13 years 9 months ago
Structural Coverage For LOTOS - a Probe Insertion Technique
Coverage analysis of programs and specifications is a common approach to measure the quality and the adequacy of a test suite. This paper presents a probe insertion technique for m...
Daniel Amyot, Luigi Logrippo
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 8 months ago
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing
Abstract--A novel input and output biasing circuit to extend the input common mode (CM) voltage range and the output swing to rail-to-rail in a low voltage op-amp in standard CMOS ...
S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Pan...