78 search results - page 11 / 16 » Instruction Cache Fetch Policies for Speculative Execution |
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To...
ICS
1995
Tsinghua U.
13 years 11 months ago
1995
Tsinghua U.
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
ISCA
2002
IEEE
13 years 7 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
ICS
1998
Tsinghua U.
13 years 12 months ago
1998
Tsinghua U.
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we propose a fully automatic dynamic scratchpad memory (SPM) management technique for instructions. Our technique loads required code segments into the SPM on deman...