78 search results - page 5 / 16 » Instruction Cache Fetch Policies for Speculative Execution |
HPCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
ICPP
1999
IEEE
13 years 12 months ago
1999
IEEE
Instruction fetch bandwidth is feared to be a major limiting factor to the performance of future wide-issue aggressive superscalars. In this paper, we focus on Database applicatio...
HPCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...