174 search results - page 6 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
IEEEPACT
1999
IEEE
13 years 11 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
ACMMSP
2004
ACM
14 years 27 days ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
CATA
2004
13 years 8 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
IPCCC
1999
IEEE
13 years 11 months ago
1999
IEEE
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...