1192 search results - page 18 / 239 » Instruction Level Distributed Processing |
IJCSA
2008
13 years 6 months ago
2008
ADAPTAPlan project provides dynamic assistance for reducing authors' effort in developing instructional design tasks using user modelling, planning and machine learning techn...
IEEEPACT
2005
IEEE
14 years 10 days ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
IPPS
2005
IEEE
14 years 10 days ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
HPCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Traditional DMA requires the operating system to perform many tasks to initiate a transfer, with overhead on the order of hundreds or thousands of CPU instructions. This paper des...
ASPDAC
2006
ACM
14 years 21 days ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...