2784 search results - page 100 / 557 » Instruction Level Parallelism |
118
Voted
ISCA
1992
IEEE
15 years 6 months ago
1992
IEEE
A quantitative analysis of program execution is essential to the computer architecture design process. With the current trend in architecture of enhancing the performance of unipr...
124
Voted
SSIAI
2000
IEEE
15 years 7 months ago
2000
IEEE
This paper describes a content-based image retrieval system that employs both higher-level and lower-level vision methodologies separately and in conjunction for the retrieval of ...
106
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IPPS
2000
IEEE
15 years 7 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
109
Voted
ASAP
2007
IEEE
15 years 4 months ago
2007
IEEE
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
133
Voted
SAMOS
2004
Springer
15 years 8 months ago
2004
Springer
— In this paper we present the Molen programming paradigm, which is a sequential consistency paradigm for programming Custom Computing Machines (CCM). The programming paradigm al...