2784 search results - page 103 / 557 » Instruction Level Parallelism |
154
Voted
FPL
2010
Springer
15 years 18 days ago
2010
Springer
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
114
Voted
WWW
2003
ACM
16 years 3 months ago
2003
ACM
The use of dynamically generated Web content is gaining in popularity over traditional static HTML content. Dynamic Web content is generated on the fly according to the instructio...
139
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SODA
2001
ACM
15 years 4 months ago
2001
ACM
We consider the problem of scheduling unit-length jobs on identical parallel machines such that the makespan of the resulting schedule is minimized. Precedence constraints impose ...
110
Voted
ISHPC
2003
Springer
15 years 7 months ago
2003
Springer
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
124
Voted
HPCA
2000
IEEE
15 years 7 months ago
2000
IEEE
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...