2784 search results - page 11 / 557 » Instruction Level Parallelism |
EUC
2005
Springer
14 years 3 months ago
2005
Springer
Abstract. Embedded systems have strict timing and code size requirements. Retiming is one of the most important optimization techniques to improve the execution time of loops by in...
IPPS
2003
IEEE
14 years 3 months ago
2003
IEEE
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
ASAP
2006
IEEE
14 years 3 months ago
2006
IEEE
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
ICS
2009
Tsinghua U.
14 years 4 months ago
2009
Tsinghua U.
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...