2784 search results - page 17 / 557 » Instruction Level Parallelism |
LCTRTS
2007
Springer
14 years 4 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
MASCOTS
2010
13 years 11 months ago
2010
Abstract--We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the na...
CAMP
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
HPCA
2003
IEEE
14 years 10 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
HPCA
1996
IEEE
14 years 2 months ago
1996
IEEE
Traditional DMA requires the operating system to perform many tasks to initiate a transfer, with overhead on the order of hundreds or thousands of CPU instructions. This paper des...