2784 search results - page 21 / 557 » Instruction Level Parallelism |
HICSS
1995
IEEE
14 years 1 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
HPCA
2005
IEEE
14 years 10 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
WMPI
2004
ACM
14 years 3 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
PARELEC
2006
IEEE
14 years 3 months ago
2006
IEEE
CGO
2007
IEEE
14 years 4 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...