2784 search results - page 22 / 557 » Instruction Level Parallelism |
TJS
2002
13 years 9 months ago
2002
Although it is increasingly difficult for large scientific programs to attain a significant fraction of peak performance on systems based on microprocessors with substantial instr...
HPCA
2000
IEEE
14 years 2 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
ISCAS
2005
IEEE
14 years 3 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
EDO
2000
Springer
14 years 1 months ago
2000
Springer
Abstract Designing and maintaining a distributed system requires consideration of dependencies and invariants in the system's model. This paper suggests expressing distributio...
ICS
1995
Tsinghua U.
14 years 1 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...