Sciweavers

2784 search results - page 39 / 557
» Instruction Level Parallelism
Sort
View
HPCA
1998
IEEE
14 years 2 months ago
Speculative Versioning Cache
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, G...
FLAIRS
2004
13 years 11 months ago
PIModel: A Pragmatic ITS Model Based on Instructional Automata Theory
It is a vital and challenging issue in AI community to get the "Right Information" to the "Right People" in the "Right Language" in the "Right T...
Jinxin Si, Xiaoli Yue, Cungen Cao, Yuefei Sui
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
14 years 1 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
DATE
2005
IEEE
138views Hardware» more  DATE 2005»
13 years 12 months ago
BB-GC: Basic-Block Level Garbage Collection
Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze la...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin