2784 search results - page 41 / 557 » Instruction Level Parallelism |
ICPP
2008
IEEE
14 years 4 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
HPCA
2001
IEEE
14 years 10 months ago
2001
IEEE
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hi...
ASPLOS
2009
ACM
14 years 10 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...