2784 search results - page 46 / 557 » Instruction Level Parallelism |
IPPS
2008
IEEE
14 years 4 months ago
2008
IEEE
This paper describes the outcomes of the NSF Grant CNS-0615085: CSR-EHS: Enhancing the Effectiveness of Utilizing an Instruction Register File. We improved promoting instructions ...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
ISCA
1992
IEEE
14 years 2 months ago
1992
IEEE
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
OHS
2001
Springer
14 years 2 months ago
2001
Springer
Abstract. In this paper we present the architecture of an Adaptive Educational Hypermedia System, named INSPIRE. This particular system, throughout its interaction with the learner...
CLUSTER
2007
IEEE
14 years 4 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...