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» Instruction Level Parallelism
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CASES
2001
ACM
14 years 1 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
CGO
2003
IEEE
14 years 3 months ago
Phi-Predication for Light-Weight If-Conversion
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...
Weihaw Chuang, Brad Calder, Jeanne Ferrante
ISCA
1999
IEEE
105views Hardware» more  ISCA 1999»
14 years 2 months ago
The Program Decision Logic Approach to Predicated Execution
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
David I. August, John W. Sias, Jean-Michel Puiatti...
JUCS
2007
86views more  JUCS 2007»
13 years 9 months ago
Improving LO Quality through Instructional Design Based on an Ontological Model and Metadata
: The activities developed in this paper were aimed at providing an awareness of the elements that should be considered in quality learning objects instructional design for elearni...
Erla Morales Morgado, Francisco José Garc&i...
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
14 years 4 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...