2784 search results - page 58 / 557 » Instruction Level Parallelism |
ICCAD
1994
IEEE
14 years 2 months ago
1994
IEEE
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
CASES
2005
ACM
13 years 12 months ago
2005
ACM
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs). This is a generalized methodology for inline monitoring insec...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper explores the correlation of instruction counts and cache misses to runtime performance for a large family of divide and conquer algorithms to compute the Walsh–Hadama...
IEEEPACT
2002
IEEE
14 years 2 months ago
2002
IEEE
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...