2784 search results - page 59 / 557 » Instruction Level Parallelism |
HIPEAC
2009
Springer
14 years 1 months ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
ISPDC
2010
IEEE
13 years 8 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
IPPS
2005
IEEE
14 years 3 months ago
2005
IEEE
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
MM
2003
ACM
14 years 3 months ago
2003
ACM
In this paper, we propose a novel solution for segmenting an instructional video into hierarchical topical sections. Incorporating the knowledge of education-oriented film theory...
DAC
2009
ACM
14 years 11 months ago
2009
ACM
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...