2784 search results - page 5 / 557 » Instruction Level Parallelism |
IEEEPACT
2002
IEEE
14 years 2 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
IPPS
2000
IEEE
14 years 2 months ago
2000
IEEE
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
ICPPW
2006
IEEE
14 years 3 months ago
2006
IEEE
Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
ISHPC
1999
Springer
14 years 2 months ago
1999
Springer
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...
IJPP
2000
13 years 9 months ago
2000
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...