2784 search results - page 63 / 557 » Instruction Level Parallelism |
HPCA
1999
IEEE
14 years 2 months ago
1999
IEEE
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
ICS
1999
Tsinghua U.
14 years 2 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
DAC
1996
ACM
14 years 2 months ago
1996
ACM
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
We present a novel technique to secure the execution of a processor against the execution of malicious code (trojans, viruses). The main idea is to permute parts of the opcode val...
ECOOPW
1998
Springer
14 years 2 months ago
1998
Springer
Abstract. We introduce a collection of high performance kernels for basic linear algebra. The kernels encapsulate small xed size computations in order to provide building blocks fo...