2784 search results - page 66 / 557 » Instruction Level Parallelism |
JPDC
2000
13 years 9 months ago
2000
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
DAGSTUHL
2006
13 years 11 months ago
2006
Abstract. Within Self-reconfiguring systems two basic problems arise: on instruction level, reconfigurable instruction sets make program generation and execution inherently difficu...
ICPP
1993
IEEE
14 years 2 months ago
1993
IEEE
Abstract — In MIMD (Multiple Instruction stream, Multiple Data stream) execution, each processor has its own state. Although these states are generally considered to be independe...
EUROPAR
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Modern microprocessors have sacrificed the exactness of exceptions for improved performance long ago. This is a side effect of reordering instructions so that the micropr...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex micro-architectures combined with heavy time-to-market pressure have forced ...