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» Instruction Precomputation for Fault Detection
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ISCAPDCS
2001
13 years 8 months ago
Tolerating Transient Faults through an Instruction Reissue Mechanism
In this paper, we propose a fault-tolerant mechanism for microprocessors, which detects transient faults and recovers from them. There are two driving force to investigate fault-t...
Toshinori Sato, Itsujiro Arita
EDCC
2006
Springer
13 years 11 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
DSN
2008
IEEE
14 years 1 months ago
Trace-based microarchitecture-level diagnosis of permanent hardware faults
As devices continue to scale, future shipped hardware will likely fail due to in-the-field hardware faults. As traditional redundancy-based hardware reliability solutions that ta...
Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sah...
CLEIEJ
2006
126views more  CLEIEJ 2006»
13 years 7 months ago
Software Based Fault Tolerance against Byzantine Failures
The proposed software technique is a very low cost and an effective solution towards designing Byzantine fault tolerant computing application systems that are not so safety critic...
Goutam Kumar Saha
ASPLOS
2012
ACM
12 years 3 months ago
Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults
Future microprocessors need low-cost solutions for reliable operation in the presence of failure-prone devices. A promising approach is to detect hardware faults by deploying low-...
Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naei...