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» Instruction Precomputation for Fault Detection
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ICCD
2004
IEEE
97views Hardware» more  ICCD 2004»
14 years 4 months ago
Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution
1 Many computer security threats involve execution of unauthorized foreign code on the victim computer. Viruses, network and email worms, Trojan horses, backdoor programs used in ...
A. Murat Fiskiran, Ruby B. Lee
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
13 years 12 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
ICNP
2003
IEEE
14 years 22 days ago
Exploiting Routing Redundancy via Structured Peer-to-Peer Overlays
Structured peer-to-peer overlays provide a natural infrastructure for resilient routing via efficient fault detection and precomputation of backup paths. These overlays can respo...
Ben Y. Zhao, Ling Huang, Jeremy Stribling, Anthony...
ET
2008
92views more  ET 2008»
13 years 7 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ASPLOS
2000
ACM
13 years 11 months ago
Slipstream Processors: Improving both Performance and Fault Tolerance
Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effec...
Karthik Sundaramoorthy, Zachary Purser, Eric Roten...