18 search results - page 2 / 4 » Instruction Replication for Clustered Microarchitectures |
IPPS
2005
IEEE
14 years 29 days ago
2005
IEEE
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
In this work we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating...
SPAA
2006
ACM
14 years 1 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
SBACPAD
2005
IEEE
14 years 29 days ago
2005
IEEE
The time required to simulate a complete benchmark program using the cycle-accurate model of a microprocessor can be prohibitively high. One of the proposed methodologies, represe...