113 search results - page 10 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
APCSAC
2005
IEEE
14 years 1 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- a...
EUROPAR
2004
Springer
14 years 27 days ago
2004
Springer
Scheduling parallel jobs has been an active investigation area. The scheduler has to deal with heterogeneous workloads and try to obtain throughputs and response times such that en...