113 search results - page 11 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
CASES
2009
ACM
14 years 2 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
ANCS
2009
ACM
13 years 5 months ago
2009
ACM
Ubiquitous multi-core-based web servers and edge routers are increasingly popular in deploying computationally intensive Deep Packet Inspection (DPI) programs. Previous work has s...
CIMCA
2008
IEEE
14 years 2 months ago
2008
IEEE
—The computational grid provides a promising platform for the deployment of various high-performance computing applications. In computational grid, an efficient scheduling of tas...
SAC
2004
ACM
14 years 28 days ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...