113 search results - page 2 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
ASAP
2000
IEEE
13 years 11 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
VLSID
2008
IEEE
14 years 7 months ago
2008
IEEE
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
HPDC
2010
IEEE
13 years 7 months ago
2010
IEEE
Parallel computing on volatile distributed resources requires schedulers that consider job and resource characteristics. We study unconventional computing environments containing ...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...