138 search results - page 8 / 28 » Instruction Scheduling and Executable Editing |
MICRO
1991
IEEE
13 years 11 months ago
1991
IEEE
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
MICRO
1991
IEEE
13 years 11 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
PLDI
2006
ACM
14 years 1 months ago
2006
ACM
In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a ...
ASPLOS
1992
ACM
14 years 5 hour ago
1992
ACM
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
APCSAC
2001
IEEE
13 years 11 months ago
2001
IEEE
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...