Executing Loops on a Fine-Grained MIMD Architecture

- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processors as well as pipelined nature of individual processors. The processors based upon the load/store architecture read/write operands frotn/to private registers, shared registers, and channel queues. If the communication of a vahte from one processor to another requires synchronization then a channel is used otherwise a shared register is used to communicate the vahte. The reeeiving processor reads the values from a channel queue in the order they are written to the channel by the sending processor. The scheduling of operations is carried out in a manner that reduces interprocessor communication. Such schedules reduce the likelihood of one processor impeding the progress of other processors.

• Type: Conference
• Year: 1991
• Where: MICRO
• Authors: Sunah Lee, Rajiv Gupta
• Keywords: Architecture Read/write Operands, Channel Queue, Hardware, MICRO 1991, Shared Register