91 search results - page 17 / 19 » Instruction Selection for Compilers that Target Architecture... |
JPDC
2000
13 years 7 months ago
2000
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
CGO
2003
IEEE
14 years 27 days ago
2003
IEEE
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
IWOMP
2007
Springer
14 years 1 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...