91 search results - page 9 / 19 » Instruction Selection for Compilers that Target Architecture... |
CGO
2007
IEEE
14 years 1 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...