369 search results - page 13 / 74 » Instruction set mapping for performance optimization |
114
Voted
CODES
2005
IEEE
15 years 8 months ago
2005
IEEE
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...
135
Voted
ICS
1999
Tsinghua U.
15 years 7 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
132
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CASES
2006
ACM
15 years 8 months ago
2006
ACM
In this paper, we propose a fully automatic dynamic scratchpad memory (SPM) management technique for instructions. Our technique loads required code segments into the SPM on deman...
147
Voted
EH
2004
IEEE
15 years 6 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
149
Voted
CASES
2010
ACM
15 years 20 days ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...