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HOTI
2008
IEEE
15 years 11 months ago
HPP Switch: A Novel High Performance Switch for HPC
The high performance switch plays a critical role in the high performance computer (HPC) system. The applications of HPC not only demand on the low latency and high bandwidth of t...
Dawei Wang, Zheng Cao, Xinchun Liu, Ninghui Sun
ICPPW
1999
IEEE
15 years 8 months ago
Performance Evaluation of Public-Key Certificate Revocation System with Balanced Hash Tree
A new method for updating certificate revocation trees (CRT) is proposed. Efficient revocation of publickey certificates is a current issue in public-key Infrastructure because a ...
Hiroaki Kikuchi, Kensuke Abe, Shohachiro Nakanishi
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 8 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
CF
2004
ACM
15 years 10 months ago
Improving the execution time of global communication operations
Many parallel applications from scientific computing use MPI global communication operations to collect or distribute data. Since the execution times of these communication opera...
Matthias Kühnemann, Thomas Rauber, Gudula R&u...
ICPP
2007
IEEE
15 years 10 months ago
CPU MISER: A Performance-Directed, Run-Time System for Power-Aware Clusters
Performance and power are critical design constraints in today’s high-end computing systems. Reducing power consumption without impacting system performance is a challenge for t...
Rong Ge, Xizhou Feng, Wu-chun Feng, Kirk W. Camero...