This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
Previous work proposed a technique for predicting problems resulting from replacing one version of a software component by another. The technique reports, before performing the rep...
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
One of the interesting problems in hardware-software co-design is that of debugging embedded software in conjunction with hardware. Currently, most software designers wait until a...
A. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Ja...
The elimination of induction variables and the parallelization of reductions in FORTRAN programs have been shown to be integral to performance improvement on parallel computers 7,...