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GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
ECOOP
2004
Springer
13 years 11 months ago
Early Identification of Incompatibilities in Multi-component Upgrades
Previous work proposed a technique for predicting problems resulting from replacing one version of a software component by another. The technique reports, before performing the rep...
Stephen McCamant, Michael D. Ernst
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
13 years 11 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
ASPDAC
1995
ACM
111views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A hardware-software co-simulator for embedded system design and debugging
One of the interesting problems in hardware-software co-design is that of debugging embedded software in conjunction with hardware. Currently, most software designers wait until a...
A. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Ja...
ICS
1995
Tsinghua U.
13 years 11 months ago
Idiom Recognition in the Polaris Parallelizing Compiler
The elimination of induction variables and the parallelization of reductions in FORTRAN programs have been shown to be integral to performance improvement on parallel computers 7,...
William M. Pottenger, Rudolf Eigenmann