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CEC
2009
IEEE
13 years 11 months ago
JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...
Olivier Brousse, Jérémie Guillot, Th...
CONCURRENCY
2010
130views more  CONCURRENCY 2010»
13 years 7 months ago
Enabling high-speed asynchronous data extraction and transfer using DART
As the complexity and scale of current scientific and engineering applications grow, managing and transporting the large amounts of data they generate is quickly becoming a signif...
Ciprian Docan, Manish Parashar, Scott Klasky
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 25 days ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
LREC
2008
150views Education» more  LREC 2008»
13 years 9 months ago
The 2008 Oriental COCOSDA Book Project: in Commemoration of the First Decade of Sustained Activities in Asia
The purpose of Oriental COCOSDA is to provide the Asian community a platform to exchange ideas, to share information and to discuss regional matters on creation, utilization, diss...
Shuichi Itahashi, Chiu-yu Tseng
BMCBI
2010
100views more  BMCBI 2010»
13 years 7 months ago
Partitioning of copy-number genotypes in pedigrees
Background: Copy number variations (CNVs) and polymorphisms (CNPs) have only recently gained the genetic community's attention. Conservative estimates have shown that CNVs an...
Louis-Philippe Lemieux Perreault, Gregor U. Andelf...