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» Integration of Simulation with Enterprise Models
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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 4 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
HPCA
2009
IEEE
14 years 10 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
BMCBI
2008
113views more  BMCBI 2008»
13 years 10 months ago
Investigating selection on viruses: a statistical alignment approach
Background: Two problems complicate the study of selection in viral genomes: Firstly, the presence of genes in overlapping reading frames implies that selection in one reading fra...
Saskia de Groot, Thomas Mailund, Gerton Lunter, Jo...
JSAC
2007
180views more  JSAC 2007»
13 years 9 months ago
A Cross-Layer Approach for WLAN Voice Capacity Planning
— This paper presents an analytical approach to determining the maximum number of on/off voice flows that can be supported over a wireless local area network (WLAN), under a qua...
Yu Cheng, Xinhua Ling, Wei Song, Lin X. Cai, Weihu...
ASPDAC
2008
ACM
127views Hardware» more  ASPDAC 2008»
13 years 12 months ago
Power grid analysis benchmarks
ACT Benchmarks are an immensely useful tool in performing research since they allow for rapid and clear comparison between different approaches to solving CAD problems. Recent expe...
Sani R. Nassif