This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
We propose a model for understanding the transformation of the market structure in the recorded music industry value chain due to new forms of digital distribution. It takes into a...
Jesse Bockstedt, Robert J. Kauffman, Frederick J. ...
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...
— Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant h...