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DFT
2005
IEEE
92views VLSI» more  DFT 2005»
14 years 1 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
HICSS
2005
IEEE
134views Biometrics» more  HICSS 2005»
14 years 1 months ago
The Move to Artist-Led Online Music Distribution: Explaining Structural Changes in the Digital Music Market
We propose a model for understanding the transformation of the market structure in the recorded music industry value chain due to new forms of digital distribution. It takes into a...
Jesse Bockstedt, Robert J. Kauffman, Frederick J. ...
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 26 days ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
EH
2003
IEEE
135views Hardware» more  EH 2003»
14 years 25 days ago
Towards Evolvable IP Cores for FPGAs
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...
Lukás Sekanina
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
14 years 25 days ago
IP Watermarking Techniques: Survey and Comparison
— Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant h...
Amr T. Abdel-Hamid, Sofiène Tahar, El Mosta...