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AHS
2007
IEEE
251views Hardware» more  AHS 2007»
13 years 11 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
ETS
2010
IEEE
130views Hardware» more  ETS 2010»
13 years 8 months ago
A distributed architecture to check global properties for post-silicon debug
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...
Erik Larsson, Bart Vermeulen, Kees Goossens
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 29 days ago
HIBI-based multiprocessor SoC on FPGA
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
ODRL
2004
13 years 8 months ago
REAP: A System for Rights Management in Digital Libraries
This paper presents REAP, a system for rights management in digital libraries. REAP is aimed at demonstrating that intellectual property can be published in the Internet by digita...
Øyvind Vestavik
CODES
2008
IEEE
14 years 1 months ago
Extending open core protocol to support system-level cache coherence
Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range...
Konstantinos Aisopos, Chien-Chun Chou, Li-Shiuan P...