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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 11 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
177
Voted
MOBIHOC
2005
ACM
16 years 2 months ago
Power balanced coverage-time optimization for clustered wireless sensor networks
We consider a wireless sensor network in which sensors are grouped into clusters, each with its own cluster head (CH). Each CH collects data from sensors in its cluster and relays...
Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula
113
Voted
AAAI
1998
15 years 3 months ago
An Architecture for Exploring Large Design Spaces
We describe an architecture for exploring very large design spaces, for example, spaces that arise when design candidates are generated by combining components systematically from...
John R. Josephson, B. Chandrasekaran, Mark Carroll...
166
Voted
BMCBI
2008
166views more  BMCBI 2008»
15 years 1 months ago
QuantPrime - a flexible tool for reliable high-throughput primer design for quantitative PCR
Background: Medium- to large-scale expression profiling using quantitative polymerase chain reaction (qPCR) assays are becoming increasingly important in genomics research. A majo...
Samuel Arvidsson, Miroslaw Kwasniewski, Diego Maur...
206
Voted
ACPC
1999
Springer
15 years 6 months ago
Optimizing I/O for Irregular Applications on Distributed-Memory Machines
In this paper we present the design, implementation and evaluation of a runtime system based on collective I/O techniques for irregular applications. Its main goal is to provide pa...
Jesús Carretero, Jaechun No, Alok N. Choudh...