154 search results - page 12 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
ISVLSI
2002
IEEE
14 years 3 months ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
VLSID
2000
IEEE
14 years 2 months ago
2000
IEEE
The technique presented here achieves simultaneous optimization of schedule time and data path component cost within a structured data path architecture, using a genetic algorithm...
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
TJS
2002
13 years 10 months ago
2002
Abstract-The current trend in constructing high-performance computing systems is to connect a large number of machines via a fast interconnect or a large-scale network such as the ...
ICCD
1994
IEEE
14 years 2 months ago
1994
IEEE
This paper presents a simple and robust method of designing the lossy-transmission-line interconnects in a network for multichip modules. This method uses wire-sizing entirely to ...