816 search results - page 105 / 164 » Interconnect design methods for memory design |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
MEMOCODE
2007
IEEE
14 years 2 months ago
2007
IEEE
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
LCPC
2005
Springer
14 years 1 months ago
2005
Springer
Thread level speculation (TLS) has shown great promise as a strategy for fine to medium grain automatic parallelisation, and in a hardware context techniques to ensure correct TLS...
CGF
2010
13 years 7 months ago
2010
The technique of Delaunay refinement has been recognized as a versatile tool to generate Delaunay meshes of a variety of geometries. Despite its usefulness, it suffers from one la...
DAC
2003
ACM
14 years 28 days ago
2003
ACM
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...