816 search results - page 34 / 164 » Interconnect design methods for memory design |
GLVLSI
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top m...
SLIP
2006
ACM
14 years 1 months ago
2006
ACM
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk ...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
Prefetching in shared-memory multiprocessor systems is an increasingly difficult problem. As system designs grow to incorporate larger numbers of faster processors, memory latency...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...