816 search results - page 68 / 164 » Interconnect design methods for memory design |
GLVLSI
2006
IEEE
14 years 3 months ago
2006
IEEE
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
GECCO
2010
Springer
14 years 1 months ago
2010
Springer
Technology scaling has offered advantages to embedded systems, such as increased performance, more available memory and reduced energy consumption. However, scaling also brings a...
ISCA
2007
IEEE
14 years 3 months ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
DAC
2000
ACM
14 years 10 months ago
2000
ACM
We describe a new method for accurate large-scale capacitance calculations. The algorithm uses an integral equation formulation, but with a new representation for charge distribut...