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DAC
2012
ACM
11 years 10 months ago
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
Myung-Chul Kim, Igor L. Markov
DAC
2009
ACM
14 years 2 months ago
Variational capacitance extraction of on-chip interconnects based on continuous surface model
In this paper we present a continuous surface model to describe the interconnect geometric variation, which improves the currently used model for better accuracy while not increas...
Wenjian Yu, Chao Hu, Wangyang Zhang
ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
14 years 4 months ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...
IPPS
1997
IEEE
13 years 11 months ago
Nearly Optimal One-To-Many Parallel Routing in Star Networks
Star networks were proposedrecently as an attractive alternative to the well-known hypercube models for interconnection networks. Extensive research has been performed that shows ...
Chi-Chang Chen, Jianer Chen
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 11 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen