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ISCA
1996
IEEE
120views Hardware» more  ISCA 1996»
14 years 29 days ago
Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-c...
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk
ASPLOS
2008
ACM
13 years 10 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
DSD
2008
IEEE
124views Hardware» more  DSD 2008»
14 years 3 months ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
ICCD
2006
IEEE
125views Hardware» more  ICCD 2006»
14 years 5 months ago
Partial Functional Manipulation Based Wirelength Minimization
—In-place flipping of rectangular blocks/cells can potentially reduce the wirelength of a floorplan/placement solution without changing the chip area, In a recent work [Hao 05], ...
Avijit Dutta, David Z. Pan
DESRIST
2009
Springer
137views Education» more  DESRIST 2009»
14 years 1 months ago
Situational method engineering for governance, risk and compliance information systems
Against the background of the current financial crisis and an aftermath of increasing regulation, companies enhance and integrate information systems in the areas of risk manageme...
Anke Gericke, Hans-Georg Fill, Dimitris Karagianni...