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IEEEPACT
2000
IEEE
14 years 1 months ago
Dynamic Branch Prediction for a VLIW Processor
This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and ...
Jan Hoogerbrugge
EUROPAR
1999
Springer
14 years 1 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
HPCA
1998
IEEE
14 years 1 months ago
The Effectiveness of SRAM Network Caches in Clustered DSMs
The frequency of accesses to remote data is a key factor affecting the performance of all Distributed Shared Memory (DSM) systems. Remote data caching is one of the most effective...
Adrian Moga, Michel Dubois
EUROPAR
2006
Springer
14 years 12 days ago
SEER: Scalable Energy Efficient Relay Schemes in MANETs
In Mobile Ad Hoc Networks (MANETs), broadcasting is widely used to support many applications. Several adaptive broadcast schemes have been proposed to reduce the number of rebroadc...
Lin-Fei Sung, Cheng-Lin Wu, Yi-Kai Chiang, Shyh-In...
PODC
2009
ACM
14 years 9 months ago
Max registers, counters, and monotone circuits
A method is given for constructing a max register, a linearizable, wait-free concurrent data structure that supports a write operation and a read operation that returns the larges...
James Aspnes, Hagit Attiya, Keren Censor