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» Internode: Internal Node Logic Computational Model
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VLSID
2005
IEEE
255views VLSI» more  VLSID 2005»
14 years 7 months ago
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...
EDCC
2010
Springer
13 years 11 months ago
Dependability Analysis of Diffusion Protocols in Wireless Networks with Heterogeneous Node Capabilities
Wireless networks are starting to be populated by interconnected devices that reveal remarkable hardware and software differences. This fact raises a number of questions on the ap...
Paolo Masci, Silvano Chiaradonna, Felicita Di Gian...
JUCS
2006
145views more  JUCS 2006»
13 years 7 months ago
Computer Science, Logic, Informatics Education
: Our aim is to discuss what, when and, how deep logic should be taught in the computer science education in connection with the so called "Bologna process". We survey th...
Katalin Pásztor-Varga, Magda Várter&...
LICS
2002
IEEE
13 years 12 months ago
Computational Adequacy for Recursive Types in Models of Intuitionistic Set Theory
This paper provides a unifying axiomatic account of the interpretation of recursive types that incorporates both domain-theoretic and realizability models as concrete instances. O...
Alex K. Simpson
INFOCOM
1993
IEEE
13 years 11 months ago
A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Multiple Node Case
Worst-casebounds on delay and backlog are derived for leaky bucket constrained sessions in arbitrary topology networks of Generalized Processor Sharing (GPS) 10] servers. The inhe...
Abhay K. Parekh, Robert G. Gallager