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GLVLSI
2005
IEEE
158views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Quantum-dot cellular automata SPICE macro model
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
Rui Tang, Fengming Zhang, Yong-Bin Kim
RSP
2003
IEEE
14 years 24 days ago
Verification of Timing Properties in Rapid System Prototyping
This paper addresses the need for systematic verification of timing properties of real-time prototypes, which consist of timing constraints that must be satisfied at any given tim...
Doron Drusinsky, Man-tak Shing
VLSID
1999
IEEE
122views VLSI» more  VLSID 1999»
13 years 11 months ago
Formal Verification of an ARM Processor
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
Vishnu A. Patankar, Alok Jain, Randal E. Bryant
SSDBM
1998
IEEE
115views Database» more  SSDBM 1998»
13 years 11 months ago
Tools for Data Warehouse Quality
In this demonstration, we show three interrelated tools intended to improve different aspects of the quality of data warehouse solutions. Firstly, the deductive object manager Con...
Michael Gebhardt, Matthias Jarke, Manfred A. Jeusf...
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...