We study modular, automatic code generation from hierarchical block diagrams with synchronous semantics. Such diagrams are the fundamental model behind widespread tools in the emb...
Roberto Lublinerman, Christian Szegedy, Stavros Tr...
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Koskenniemi's model of two-level morphology has been very influential in recent years, but definitions of the formalism have generally been phrased in terms of a compilation ...
The finite element (FE) mesh sizing has great influence on computational time, memory usage, and accuracy of FE analysis. Based on a systematic in-depth study of the geometric com...
William Roshan Quadros, Steven J. Owen, Michael L....
We propose a procedure for automated implicit inductive theorem proving for equational specifications made of rewrite rules with conditions and constraints. The constraints are int...